1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to a clock gating circuit method for area and power reduction.
2. Description of the Relevant Art
An integrated circuit (IC) chip, such as a processor or a controller, includes a synchronization of events in order to move and process data and allow sub-blocks in the design to communicate with one another. A reference is needed to provide the synchronization across the chip. Usually an IC chip includes one or more clock signals, depending on the chosen methodology, to provide this reference. This clock signal may be derived from a phase locked loop (PLL) placed on- or off-chip and provide a voltage waveform used by storage elements within the IC chip.
Due to on-chip parasitics, such as resistance and, more crucially, capacitance, the clock waveform degrades over routing distance across the chip. The farther a receiver is located from a clock source, the worse the degradation may be. In order to improve the waveform, clock buffer circuits may be located at predetermined locations, or stages, across the chip. New reference clock signals are derived at each stage from the original reference clock signal. Each storage element should receive a new reference clock signal at the same time as other storage elements. There may be some error, but the amount of this error should lie within predetermined design constraints.
Another design requirement of IC chips is lowering power. Mobile devices especially require low-power circuit techniques due to a lack of cooling devices such as fans and due to being powered by batteries. One low-power technique is the ability to disable a clock signal in a sub-block or an array when the internal circuitry is not required to perform work for an extended amount of time. Later, when the period of inactivity has ended, the clock signal is enabled again. An enable signal may be routed to a clock-gating circuit in order to perform this power-saving technique.
However, even if sub-blocks and arrays have the ability to enable and disable their respective clock signals, the total IC chip power consumption may still be high. Dynamic power of an IC chip is directly proportional to the clock frequency, the square of the operating voltage, and the on-die capacitance being charged and discharged. If the clock frequency is reduced, the IC chip power would be reduced. However, circuit activity, and thus performance, would be reduced also, and IC chip designs continue to demand higher performance. Another method to reduce power consumption is to reduce the operating voltage. Although, this method also reduces the amount of current used to charge and discharge circuit nodes, which reduces the switching speeds of circuits. Again, chip performance is reduced.
A third method to reduce chip power is to reduce the on-chip capacitance. The clock buffer circuits may be numerous on the IC chip. These clock buffer circuits, unlike circuits following a clock gated circuit, need to drive a signal every clock cycle. Many of the clock buffer circuits may be large in size due to the large capacitive load they need to drive. The clock buffer circuits drive the signal route capacitance and the logic-gate input capacitance of storage elements and combinatorial logic. Large clock buffer circuits require more current drawn from the power supply, and therefore consume more power. A common design problem is the amount of capacitance the clock buffer circuits need to drive as this greatly increases the power consumption of the chip. The spacing, width, and length of signal routes may be studied and adjusted in order to reduce the parasitic capacitance of the routes. Attempts may be taken to reduce the gate widths of the storage elements and combinatorial logic. However, both the signal route parasitic capacitance and combinatorial gate input widths may still be great due to aggressive performance goals.
Although clock gating circuits may be used to disable the clock signals to various sections of the chip in order to help reduce clock power, these same circuits may increase the logic-gate input capacitance to be driven by the clock buffer circuits. Also, these same circuits may crowd clock rows designated for clock signal routing, which leads to increased chip area and increased parasitic signal capacitance, since this route spacing is decreased.
In view of the above, an efficient method for clock gating that reduces on-chip area and power is desired.